The PCI (Peripheral Component Interconnect) bus is a standardized local-bus that is used for connection between a CPU and its peripherals. At its inception, the PCI bus was designed to allow for motherboard connection of high-speed peripherals. Soon thereafter, the PCI bus began to replace the ISA local-bus as the bus used to connect add-in cards to the motherboard CPU. The PCI bus now dominates the desktop PC (personal computer) market as the primary way of connecting peripherals to the CPU, and variants of the standard PCI bus have evolved for industrial, compact, and mobile applications.
The PCI bus and peripherals connected to the bus operate in accordance with the PCI specification, which is published by the PCI Special Interest Group ("SIG"). Because it is processor-independent, any CPU or peripheral can be connected to the bus. In accordance with revision 2.1 of the specification, the PCI bus provides a 32-bit data path running at a 33 MHz clock rate for a maximum bandwidth of 132 megabytes per second ("MB/s"). Definitions for 64-bit data path and 66 MHz clock rate options are also included in the current specification. This combination of speed and flexibility has made the PCI bus the standard interconnection method between peripherals and a host CPU.
FIG. 11 shows a block diagram of the arrangement of a host CPU and add-on peripherals in a conventional PC. The conventional PC is implemented on a motherboard MB and includes a central processing unit CPU and its associated main memory M0, which is a large block of DRAM. A cache of fast memory SRAM, logic control chip set, and CPU bus are also provided on the motherboard MB along with a PCI bus. Peripherals (C1, C2, and C3), each in the form of an add-in card, are connected to the motherboard PCI bus. In this example, the peripherals consist of an MPEG2 decoder C3, a 3-D graphics accelerator C2, and a combination 2-D graphics accelerator and VGA controller C1. The VGA controller C1 is connected to a monitor CRT. An ISA bridge may also be provided to allow ISA-based peripherals to be connected to the system.
As shown in FIG. 11, each add-on peripheral (C1, C2, or C3) can only transfer data to or from another peripheral, or to or from the large main memory M0, by using the PCI bus. However, the PCI bus may not be able to provide the type of performance required by high-bandwidth multimedia and graphics peripherals for applications such as 3-D graphics, digital audio, and motion video. For example, the three add-in cards shown in FIG. 11 will find it extremely difficult, if not impossible, to operate together over the motherboard PCI bus. While the theoretical maximum bandwidth of the PCI bus is 132 MB/s, typical sustainable throughput on the bus ranges from 40 to 80 MB/s due to factors such as bus contention. Meanwhile, for 3-D graphics, the stream of 3-D polygon information coming from the CPU can range from 10 to 15 MB/s and the resulting rendered pixel stream from the 3-D accelerator C2 will be in the range of 40 MB/s. Thus, even if the 3-D graphics accelerator has its own memory and the ability to transfer data directly to screen memory, 3-D graphics alone requires a bandwidth of over 50 MB/s.
In the case of motion video, the compressed data stream going to the MPEG2 decoder C3 is only about 1 MB/s but the uncompressed video stream is around 30 MB/s. Additionally, these two graphics applications must contend for bus bandwidth along with other transactions required for applications such as audio, CD-ROM access, hard disk access, and joystick or controller input. In fact, providing multimedia peripherals with the necessary bandwidth is made even more difficult because all requests for the PCI bus are handled based on a fairness algorithm (i.e., all peripherals have the same priority when requesting access to the PCI bus). Even if the motherboard PCI bus in a conventional PC system could provide the bandwidth required by all of the connected peripherals, it is apparent that the multimedia traffic saturates the PCI bus. In the long run, such overburdening of the PCI bus compromises system performance and makes further system upgrades impossible.
Additionally, this type of add-on architecture requires a great deal of single function memory. In order to minimize required bus bandwidth and to increase its own speed, each multimedia add-on peripheral typically has an on-card dedicated RAM memory that it can use during data processing. A major drawback exists in that the RAM provided on each peripheral card cannot be reused or reallocated for other purposes--it is single-function memory. For example, the MPEG2 decoder C3 and the 3-D graphics accelerator C2 shown in FIG. 11 each require about 2 MB of dedicated memory M3 and M2, respectively, in addition to the multi-megabyte screen memory M1 provided with the VGA controller C1. Such large single-function memories are costly and wasteful and lead to add-on peripherals that are too expensive and inflexible.
To overcome some of the bandwidth problems discussed above, physically integrated devices that combine several independent features into a single add-on peripheral card have been developed. While a physically integrated device may lower the amount of bandwidth required on the motherboard PCI bus, such a design greatly sacrifices modularity. A typical integrated device is designed to include circuitry to perform many functions. Even if only a subset of these functions is desired by a user, the cost of the device is the same because all of the functions are part of a single physical component and cannot be broken up. Thus, both the integrated device and the corresponding single peripherals must be available to satisfy different price ranges and performance levels in the marketplace. Further, for each combination of features that is desired to be integrated, a separate and distinct integrated device must be designed, produced, and supported.
Thus, in a conventional PC, multimedia peripherals connected to the motherboard PCI bus saturate the PCI bus and are expensive due to large single-function memories and/or a lack of modularity. Furthermore, the PCI bus may not be able to provide the bandwidth presently required by a modest combination of multimedia peripherals--let alone accommodate future upgrades to the system to improve performance or provide additional functions.